Microprocessor devices are currently being used in a wide number of applications. As the speed of operation of microprocessor devices increases and as the cost of such devices decreases, the number of applications for such devices is extended. Typically, such microprocessor devices are coupled to a clock signal which is used to synchronize operations within the microprocessor device. The clock signal defines periodic processor cycles during which various internal operations take place. The microprocessor device operates under the control of a stored program which consists of a plurality of processor instructions. Generally, one or more processor cycles are required to fetch each instruction from the stored program and to implement each instruction. Thus, by reducing the number of processor cycles required to implement particular instructions, the overall speed of operation of a microprocessor device can be increased.
Many prior art microprocessor devices are designed to operate upon 8-bit data words and 16-bit address words. An example of one such prior art microprocessor device is the MC6800 microprocessor provided by Motorola, Inc. which is generally described in U.S. Pat. No. 4,030,079 "Processor Including Incrementer and Program Register Structure" issued to Bennett et al and assigned to the assignee of the present invention. The instruction set for this prior art microprocessor includes an addressing mode known as indexed addressing. In this mode, an 8-bit operand stored in the program memory is added to the contents of a 16-bit index register to generate the address of a memory location where an operand is stored. This prior art microprocessor also includes a mode of addressing known as relative addressing, typically used with branch instructions, wherein the address of the next instruction to be executed is computed by adding an 8-bit operand in the form of a 2's-complement number to the contents of a 16-bit program counter.
In prior art microprocessor devices that employ an 8-bit ALU (arithmetic-logic unit), instructions which require the addition of an 8-bit operand to a 16-bit operand are performed in the following manner. During a first processor cycle, the 8-bit operand and the least significant byte of the 16-bit operand are provided to the input ports of the 8-bit ALU to generate the least significant byte of the result. As is well known in the art, a byte equals 8 bits. The operation performed by the ALU may generate a carry-out if the 8-bit operand is a positive number, or it may indicate a borrow if the 8-bit operand is a 2's-complement negative number. In this case, the most significant byte of the 16-bit operand must be incremented or decremented accordingly. During a second processor cycle, the most significant byte of the 16-bit operand is transferred to an increment/decrement network which modifies the most significant byte of the 16-bit operand if a carry or borrow occurred during the first processor cycle. Finally, during a third processor cycle, the most significant byte of the result has stabilized, and the 16-bit result can then be transmitted to the stored program memory to fetch an operand or a next instruction.
It will be appreciated by those skilled in the art that a circuit and a method for reducing the number of processor cycles required to perform the above described addition of an 8-bit operand to a 16-bit operand will result in faster overall speed of operation and represents a significant improvement over the prior art.